8 bit universal shift register verilog code

So we have two ways in which data can ‘flow’ through a shift register. Similarly, each flip-flop can have its own output too. This particular setting of giving input is known as parallel input. The output is in the same order as the input. We get the data output at the last flip-flop.

Each bit passes through the cascade in a line. We can feed and extract data to and from a shift register in two ways:

Some commonly available shift registers.How to design a 4-bit Parallel in Serial Out shift register (PISO)?.How to design a 4-bit Parallel in Parallel Out shift register (PIPO)?.How to design a 4-bit Serial In Parallel Out shift register (SIPO)?.